The present invention relates to a semiconductor device and a method of fabricating the semiconductor device, a circuit board, and an electronic instrument.
As one type of CSP (Chip Scale/Size Package) semiconductor devices, a semiconductor device with a structure in which a semiconductor chip is mounted face-down to a substrate has been known. In such a face down structure, a semiconductor chip is generally mounted on a surface of the substrate on which an interconnecting pattern is formed. Therefore, since part of the interconnecting pattern is covered with the semiconductor chip, the degree of freedom in designing the interconnecting pattern is limited.
The present invention has been achieved to solve this problem. An objective of the present invention is to provide a semiconductor device and a method of fabricating the same capable of increasing the degree of freedom in designing an interconnecting pattern without decreasing connection reliability, a circuit board, and an electronic instrument.
(1) According to the present invention, there is provided a semiconductor device comprising:
a substrate including a plurality of holes and a surface over which an interconnecting pattern is formed, part of the interconnecting pattern extending over the holes;
a semiconductor chip disposed over another surface of the substrate and including a plurality of electrodes to be positioned over the holes; and
conductive members provided within the holes for electrically connecting the electrodes to the interconnecting pattern.
According to the present invention, the conductive members formed on the electrodes of the semiconductor chip are disposed within the holes and connected to the interconnecting pattern. Therefore, the interconnecting pattern is located on the side of the substrate opposite to the mounting region of the semiconductor chip. Specifically, since the interconnecting pattern is not covered with the semiconductor chip, the interconnecting pattern can be designed without limitation. Moreover, there is a substrate between the interconnecting pattern and the semiconductor chip. Therefore, signals in an integrated circuit in the semiconductor chip scarcely interfere with signals in the interconnecting pattern, whereby cross talk can be reduced. Because of this, a semiconductor device with an increased degree of freedom in designing the interconnecting pattern can be obtained without decreasing connection reliability.
(2) In this semiconductor device, a resin may be provided between the substrate and the semiconductor chip.
According to this semiconductor device, the semiconductor chip is mounted on a surface of the substrate on which the interconnecting pattern is not required, and a resin is provided between the substrate and the semiconductor chip. Therefore, if an interconnecting pattern is not formed over the surface of the substrate over which the semiconductor chip is mounted, the resin is provided on the substrate exhibiting comparatively excellent adhesion, so that delamination can be reduced. Because of this, a semiconductor device with an increased degree of freedom in designing the interconnecting pattern can be obtained more effectively without decreasing connection reliability.
(3) In this semiconductor device, the resin may be an anisotropic conductive material containing conductive particles; and the conductive members may be electrically connected to the interconnecting pattern through the conductive particles.
(4) In this semiconductor device, part of the interconnecting pattern may close the holes.
(5) In this semiconductor device, the interconnecting pattern may include a plurality of interconnecting lines; and
two or more interconnecting lines may extend over each of the holes.
This enables holes necessary for the substrate can be easily formed.
(6) In this semiconductor device, the other surface of the substrate may be roughed.
Since a contact area between the resin and the substrate is increased, adhesion between them can be further improved.
(7) In this semiconductor device, a recognition hole may be formed in the substrate at a position differing from the holes; and
a recognition pattern may be formed over the recognition hole on the side of a surface of the substrate including the interconnecting pattern.
This enables to mount the semiconductor chip easily over the substrate.
(8) In this semiconductor device, the recognition hole may be formed in the substrate outside a mounting region for the semiconductor chip.
This makes it possible to mount the semiconductor chip easily over the substrate.
(9) In this semiconductor device, the recognition pattern may includes:
a first pattern extending in the X-axis direction of the two-dimensional coordinate system established on a surface of the substrate; and
a second pattern extending in the Y-axis direction.
This enables the semiconductor chip to be accurately mounted at a given position on the substrate by recognizing the first and second patterns.
(10) In this semiconductor device, the conductive members may be a plurality of layered bumps.
This enables the conductive members to be formed by using existing techniques and devices, for example.
(11) In this semiconductor device, the bumps may include first bumps formed on the electrodes and second bumps formed on the first bumps.
Note that the first and second bumps refer to two arbitrary bumps, and this is applicable to two or more bumps.
(12) In this semiconductor device, at least the first bumps may be ball bumps.
According to this semiconductor device, the first bumps may be formed by the ball bump method. Since existing wire bonder devices can be utilized, the semiconductor device can be fabricated with reduced equipment investment.
(13) In this semiconductor device, the second bumps may be formed of a metal which has a melting point lower than the melting point of the first bumps.
According to this semiconductor device, since the first bumps formed in advance have a higher melting point, the first bumps are less affected by heat for forming the second bumps, for example. Therefore, a plurality of bumps can be easily layered.
(14) In this semiconductor device, the first bumps may be formed of gold.
Gold has a comparatively high melting point.
(15) In this semiconductor device, the second bumps may be formed of solder.
(16) In this semiconductor device, the first bumps and the second bumps may be formed of the same material.
This enables the second bump to also be formed by the ball bump method, for example.
(17) In this semiconductor device, the semiconductor chip may be mounted face-down to the substrate.
According to this semiconductor device, the interval between the semiconductor chip and the substrate is increased by the height of the first and second bumps formed on the electrodes of the semiconductor chip, so a large amount of resin can be provided right under the semiconductor chip, thereby enabling the resin to fully function as a stress relaxation layer. If the first bump is formed of gold and the second bump is formed of solder, a mounting structure of solder bumps with a core (gold) can be easily obtained.
(18) According to the present invention, there is provided a circuit board over which the above-described semiconductor device is mounted.
(19) An electronic instrument according to the present invention is provided with the above semiconductor device.
(20) According to the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
preparing a substrate including a plurality of holes and an interconnecting pattern which extends partially over the holes, and also preparing a semiconductor chip having a plurality of electrodes which have conductive members formed on the electrodes; and
disposing the conductive members within the holes and mounting the semiconductor chip over the substrate to connect electrically the interconnecting pattern to the electrodes through the conductive members.
According to the present invention, the conductive members formed on the electrodes of the semiconductor chip are disposed within the holes and connected to the interconnecting pattern. Therefore, the interconnecting pattern is located on the side of the substrate opposite to the mounting region of the semiconductor chip. Specifically, since the interconnecting pattern is not covered with the semiconductor chip, the interconnecting pattern can be designed without limitation. Moreover, there is a substrate between the interconnecting pattern and the semiconductor chip. Therefore, signals in an integrated circuit in the semiconductor chip scarcely interfere with signals in the interconnecting pattern, whereby cross talk can be reduced. Because of this, a semiconductor device with an increased degree of freedom in designing the interconnecting pattern can be obtained without decreasing connection reliability.
(21) This method of fabricating a semiconductor device may further comprise a step of providing a resin over the substrate in a region for mounting the semiconductor chip.
According to this semiconductor device, the semiconductor chip is mounted on a surface of the substrate on which the interconnecting pattern is not required, and a resin is provided between the substrate and the semiconductor chip. Therefore, if an interconnecting pattern is not formed over the surface of the substrate over which the semiconductor chip is mounted, the resin is provided on the substrate exhibiting comparatively excellent adhesion, so that interface delamination can be reduced by the heat in the mounting process. Because of this, a semiconductor device with an increased degree of freedom in designing the interconnecting pattern can be obtained more effectively without decreasing connection reliability.
(22) In this method of fabricating a semiconductor device,
the resin may be an anisotropic conductive material containing conductive particles; and
after the provision of the resin, the conductive members may be electrically connected to the interconnecting pattern through the conductive particles.
This enables the electrodes of the semiconductor chip to be electrically connected to the interconnecting pattern through the anisotropic conductive material, and, at the same time, the semiconductor chip and the substrate can be underfilled. Therefore, a semiconductor device can be fabricated using a method excelling in productivity.
(23) In this method of fabricating a semiconductor device,
the holes may be formed in the substrate to be positioned under the electrodes;
part of the interconnecting pattern may close the holes; and
the conductive members may be disposed within the holes.
(24) In this method of fabricating a semiconductor device,
the interconnecting pattern may include a plurality of interconnecting lines;
two or more of the interconnecting lines may extend over each of the holes in the substrate; and
two or more of the conductive members may be disposed within each of the holes.
This enables to easily form holes necessary for the substrate.
(25) In this method of fabricating a semiconductor device,
the step of providing a resin may include a step of mounting the substrate over a member;
the member may have properties which repel the resin at least in a region facing the holes in the substrate; and
the resin may be provided after the mounting of the substrate over the member with a surface of the substrate having the interconnecting pattern to face the member.
This enables the resin to be provided on the substrate without leaking out from slits.
(26) This method of fabricating a semiconductor device may further comprise a step of roughing the other surface of the substrate.
According to this method, since a contact area between the substrate and the resin increases, adhesion between the resin and the substrate can be further improved.
(27) This method of fabricating a semiconductor device may further comprise a step of forming a recognition hole in the substrate at a position differing from the holes, and forming a recognition pattern over the recognition hole on the side of a surface of the substrate including the interconnecting pattern.
This enables the semiconductor chip to be easily mounted over the substrate.
(28) In this method of fabricating a semiconductor device,
the recognition pattern may include a first pattern extending in the X-axis direction of the two-dimensional coordinate system established on a surface of the substrate, and a second pattern extending in the Y-axis direction; and
positioning of the semiconductor chip and the substrate may be carried out by using the recognition pattern.
This enables the semiconductor chip to be accurately mounted at a given position over the substrate by recognizing the first and second patterns.
(29) In this method of fabricating a semiconductor device,
the conductive members may be a plurality of layered bumps.
This enables the conductive members to be reliably formed.
(30) In this method of fabricating a semiconductor device, the bumps may be formed by:
a first step of bonding a first conductive wire to one of the electrodes of the semiconductor chip and cutting the bonded first conductive wire with part of the first conductive wire to remain on the one of the electrodes;
a second step of forming a first bump by pressing the remaining part of the first conductive wire on the electrode;
a third step of bonding a second conductive wire to the at first bump and cutting the bonded second conductive wire with part of the second conductive wire to remain on the first bump; and
a fourth step of forming a second bump by pressing the remaining part of the second conductive wire on the first bump.
According to this method, the first and second bumps can be layered merely by bonding the first or second conductive wire on the electrode or first bump, cutting the conductive wire while allowing part of the conductive wire to remain on the electrode or first bump, and pressing the remaining conductive wire. These steps can be performed in a short period of time in comparison with the case of layering the bumps by plating.
Note that the first and second bumps refer to two arbitrary bumps, and this is applicable to two or more bumps.
(31) In this method of fabricating a semiconductor device,
the first step may be repeated for the plurality of electrodes to provide each of the electrodes with part of the first conductive wire; and
the remaining parts of the first conductive wires on the electrodes may be simultaneously pressed to form the first bumps at a time in the second step.
According to this method, since a plurality of first bumps can be formed at the same time, the number of steps can be further reduced.
(32) In this method of fabricating a semiconductor device,
the third step may be repeated to provide each of the first bumps with part of the second conductive wire; and
the remaining parts of the second conductive wires on the electrodes may be simultaneously pressed to form the second bumps at a time in the fourth step.
According to this method, since a plurality of second bumps can be formed at the same time, the number of steps can be further reduced.